Eine Test- und Ansteuerschaltung für eine neuartige 3D Verbindungstechnologie

In der vorliegenden Arbeit wird eine Built-In Self-Test Schaltung (BIST) vorgestellt, welche die vertikalen Inter-Chip-Verbindungen in einer neuartigen 3D Schaltungstechnologie auf ihre Funktionalität zur Datenübertragung überprüft. Die 3D Technologie beruht auf der Stapelung mehrerer aktiver Silizium-CMOS-ICs, welche durch das Siliziumsubstrat hindurch vertikal miteinander elektrisch verbunden sind. Bei diesen Vias sind die zu erwartenden Defekte hochohmige Verbindungen und Kurzschlüsse. </p><p style=&quot;line-height: 20px;&quot;> Die entwickelte Testschaltung ermöglicht es, beliebige Konstellationen von vertikalen Verbindungen auf Fehler zu untersuchen, und das Ergebnis entweder zur Analyse der 3D Technologie auszulesen oder innerhalb des Chipstapels zu verwenden, um defekte Vias zu umgehen. Die Schaltung wurde in einer 0,13μm Technologie entworfen und simuliert. Ein Testchip ist momentan in Produktion

Yield-improving test and routing circuits for a novel 3-D interconnect technology

This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high. <P> The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production

Hybrid VLSI Implementation of an Associative Memory Based on Distributed Storage of Information

Rückert U, Goser K, Ramacher U. Hybrid VLSI Implementation of an Associative Memory Based on Distributed Storage of Information. In: Goser K, Ramacher U, Rückert U, eds. Proceedings of the 1st International Workshop on Microelectronics for Nerual Networks. University Dortmund, Germany; 1990: 196-203

Parallel Implementation Of Neural Associative Memories On RISC Processors

this paper we report on a case study addressing the problem of implementing NAMs on general purpose microprocessors. After a short introduction to the architecture of NAMs we will give an efficient algorithm for their parallel implementation on single microprocessors. This algorithm was mapped to well known standard microprocessors (MC88xxx, ARM2, Sparc, RS/6000, MC68xxx and Intel 286/486) which will be compared in respect to the number of connections per second (CPS) in the recall phase of the NAM. The paper concludes with a discussion of the main results of this case study